The SystemVerilog Social Club organizes casual events for professionals in the digital IC verification and design spaces (FPGA, ASIC, CPLD), with a direct focus on SystemVerilog / UVM (Universal Verification Methodology) users. Events might be unfocused social gatherings, but typically will be group code-collaboration on examples from a certain realm of SystemVerilog or digital design. Events are often centered around food & drinks. A network beyond those in our daily workplaces is undoubtedly useful when it comes to hiring, looking for new opportunities, or getting feedback on a technical problem. Online networking is great. However, face-to-face contact provides strength to just about any connection. Learning and then Networking are our goals.

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ATTENDEES:  Please do the following.   

1) Bring a laptop.   **We want you involved, not spectating.   If you cannot help find a solution to a problem online or looking at the LRM.......bad you.**

2) If you have access to a simulator, make sure you know how to access it over a public internet connection.  i.e. know how to use your vpn/vnc or whatever you need to access your simulator.    Else, take a look into edaplayground, where you can compile and simulate small amounts of code online.

3) Add a comment to the meetup comment section for a meeting indicating what topic you'd like to go over, or if you'll be bringing a question or challenge for others.   No one wants another meeting to have to prepare for, so this doesn't need to be anything formal.  It will just get others thinking about similar code snippets they might write/show in the meeting on a certain topic.

4) Bring any SystemVerilog/UVM references you rely on.

5) Join our LinkedIn group.


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If you arrive at the location and can't find/reach us, call: +1 978 257 4046.    Please don't call more than 5 minutes before the meeting starts.  I'm usually working right up until we start.

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thanks

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Recent Meetups

  • May 19 · 7:00 PM

    casual code collaboration

    4 Members

    Very informal, sitting around a table, and working thru some SystemVerilog/UVM code examples.  Do not expect a lecture.   Bring your laptop, problems, and recent revelations.
  • May 12 · 7:00 PM

    casual code collaboration

    9 Members | 1 Photo

    Very informal, sitting around a table, and working thru some SystemVerilog/UVM code examples.  Do not expect a lecture.   Bring your laptop, problems, and recent revelations.
  • May 5 · 7:00 PM

    casual code collaboration

    5 Members

    Very informal, sitting around a table, and working thru some SystemVerilog/UVM code examples.  Do not expect a lecture.   Bring your laptop, problems, and recent revelations.
  • April 21 · 7:00 PM

    casual code collaboration

    9 Members

    Very informal, sitting around a table, and working thru some SystemVerilog/UVM code examples.  Do not expect a lecture.   Bring your laptop, problems, and recent revelations.
  • March 17 · 7:00 PM

    casual code collaboration

    2 Members

    Very informal, sitting around a table, and working thru some SystemVerilog/UVM code examples.  Do not expect a lecture.   Bring your laptop, problems, and recent revelations.
  • See all past Meetups

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