The SystemVerilog Social Club organizes casual events for professionals in the digital IC verification and design spaces (FPGA, ASIC, CPLD), with a direct focus on SystemVerilog / UVM (Universal Verification Methodology) users. Events might be unfocused social gatherings, but typically will be group code-collaboration on examples from a certain realm of SystemVerilog or digital design. Events are often centered around food & drinks. A network beyond those in our daily workplaces is undoubtedly useful when it comes to hiring, looking for new opportunities, or getting feedback on a technical problem. Online networking is great. However, face-to-face contact provides strength to just about any connection. Learning and then Networking are our goals.
Future attendees. Please do the following ahead of time. Make sure that over a public wireless internet connection you can access a simulator, where you can work on some code. Bring your laptop with you and any SystemVerilog/UVM references you rely on.
If you arrive at the location and can't find/reach us, call: +1 978 257 4046.