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Learn how to design with Xilinx’s Vivado High Level Synthesis

Are High Level Synthesis tools ready for prime time? Interested in targeting your existing “C” to Xilinx All Programmable FPGAs and SoC devices? Learn how to design with Xilinx’s Vivado High Level Synthesis

Xilinx will be joining us to answer this question and introduce you to the Vivado HLS tool, which compiles C, C++ and SystemC into a synthesizable RTL module and enables seamless integration of this module into your preferred Xilinx RTL, block based or MathWorks® Simulink® model based system design environment. Attendees will gain experience on how to accelerate custom IP creation and RTL designs by leveraging existing C, C++ and SystemC specifications to be directly targeted into Xilinx All Programmable FPGA and Zynq™ SoC devices without the need to manually create RTL. The event will focus on how C -synthesis works -  scheduling/mapping resources, coding styles/guidelines, demonstration of tool usage and presentation of IP created using Vivado HLS tool.

Joining Xilinx at this event is rENIAC, Inc. rENIAC has developed hardware/software solution for the financial services applications and analytics. rENIAC will demonstrate the use of their technology to accelerate the design and deployment of low latency, high performance financial systems. Use cases for rENIAC technology include real-time market data processing, risk assessment, asset pricing and analytics


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  • Lisa W.

    Your authorized training partner Bottom Line Technologies Inc, will be hosting an HLS session in Parsipanny, NJ on 12/18-12/19. Please contact me for more details [masked] Thank you - David Greenberg for allowing me to promote.

    November 10, 2014

  • rohan p.

    Hi David. Any new plans on HLS training

    November 4, 2014

  • David G.

    June 27, 2013

  • Dilip Y.

    Hi David, will this meetup be helpful for the beginners?

    May 17, 2013

    • David G.

      I'll have to check with Xilinx; I'll post as soon as I know!

      May 18, 2013

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