- RISC-V: Delivering Open and Secure Solutions
SecureRF, Imperas and Andes are sponsoring a panel discussion on RISC-V and how it delivers open and secure solutions. Agenda: 5:30 – 6:30 PM - Networking 6:30 – 7:30 PM - Panel Discussion 3 slide introductions for each company Questions in advance are welcome 7:30 – 8:00 PM - Demos, Networking
- Catch the RISC-V SoC FPGA Wave
Microchip recently announced the first Linux capable, RISC-V based SoC FPGA architecture, PolarFire SoC. This meetup is focused on details about this architecture and understanding how to begin writing software for it. Learn about PolarFire SoC, an open, low power, programmable, RISC-V SoC FPGA architecture. Agenda: 5:30-6:20 Networking and Refreshments 6:20-6:35 Microchip - Bring Real-Time to Linux with world's first RISC-V SoC FPGA 6:35-6:50 Antmicro - Start software development for PolarFire SoC today with Renode 6:50-7:10 UltraSoC - Built in Debug Capabilities in PolarFire SoC 7:10-7:30 SiFive - Prototype RISC-V SoCs using FPGA shells 7:30-7:50 IAR - Complete Professional Development Tools for RISC-V
- RISC-V SweRV Core Deep Dive
Western Digital recently open sourced the first production grade RISC-V core, the SweRV Core EH1. At this meetup, the architecture details on this 32 bit core will be discussed. Technical experts will explain the tradeoff decisions made when developing the SweRV Core EH1, targeted applications and a technical code walk through will be shown. Agenda: 5:30-6:30 Networking & Refreshments 6:30 SweRV Core Architecture Deep Dive 7:00 SoC Level Analytics, Trace & Debug for SweRV Core Designs
- November RISC-V Bay Area Meetup hosted by Antmicro
Attend the last RISC-V Bay Area Meetup before the Inaugural RISC-V Summit in December and listen about new and exciting open source developments in the ecosystem, including Google's TensorFlow Lite on RISC-V, Antmicro's Renode and more! Schedule: 6:00-7:00 Networking with appetizers and beverages 7:00-8:30 Speakers/Demo "TensorFlow Lite on RISC-V" (Pete Warden - Google) Many emerging new microcontrollers use RISC-V, and the TensorFlow Lite team has been exploring how to best support these new platforms. In this talk, Pete Warden, Lead of the TensorFlow Mobile/Embedded team at Google will discuss how they've used Renode, gcc, and other open-source technologies to target RISC-V for machine learning. "Design Cycle Acceleration for HW/SW Co-Design with Renode" (Michael Gielda – Antmicro) Embedded systems design that involves "whole stack" co-design, including hardware, firmware, runtime (OS), and development toolchain, presents novel engineering challenges. Traditional hardware-led approaches do not work, as the software and toolchain need to co-evolve with the hardware. Dover Microsystems faced such challenges when implementing a cybersecurity product that involves both silicon IP and runtime & toolchain modifications. Dover is using the Renode open source functional simulation framework (https://renode.io) to drastically reduce their design cycle and rapidly explore architecture trade spaces. In addition, the approach enables Dover to provide a simple and effective means for customers to evaluate the entire solution, and to begin adapting their software collateral in parallel with the hardware integration effort. Antmicro will present a case study of how open-source, extensible, debuggable, and robust functional simulation has been critical to Dover’s success, and why Dover thinks Renode should become a standard part of all hardware and embedded system design and development efforts. "Making RISC-V The Most Secure Platform" (Cesare Garlati - Hex Five Security) In this session industry veteran Cesare Garlati, co-founder of Hex Five and Chief Strategist at prpl Foundation, will share the latest on RISC-V security and will offer his practitioner advice for developing secure applications. Garlati will start with an explanation of the security building blocks defined by the ISA including privileged modes and physical memory protection. He will then show how to combine these blocks to develop trusted applications with particular emphasis on IoT devices that lack MMU – and this is the capabilities of RISC-V especially shine. Finally, Garlati will introduce a breakthrough system design philosophy, entirely based on free and open standards, that allows hardware-enforced software-defined separation of data, programs and peripherals for an unlimited number of trusted execution environments. "Tim has too many projects! (RISC-V Edition)" (Tim 'mithro' Ansell - TimVideos) Tim is a long time member of the Australian open source community, where he is known for regularly giving 5 minute lightning talks with 100+ slides called "Tim has too many projects" (and way to many slides)! Having managed to escape the deadly wildlife he will now present a much more leisurely whirlwind tour through the many hardware projects he is involved with and how they now somehow all end up using RISC-V too, including: HDMI2USB (https://hdmi2usb.tv) - An open source FPGA based, conference and user group capture hardware used to record conferences around the world. LiteX Build Environment (https://github.com/timvideos/litex-buildenv/wiki) - A Python system for fast creation of architecture independent "soft CPU" based systems. FuPy (https://fupy.github.io/) - A project to allow you to do full stack development (FPGA gateware & CPU firmware) in Python! Tomu (https://tomu.im) - Open hardware microcontroller system *inside* your USB port and maybe now with more RISC-V? Come find out! There may even be hardware giveaways and crazy announcements!
- September Bay Area RISC-V Meetup
Join us for the September RISC-V Meetup hosted by Rambus!! The evening will start with a networking session, including refreshments. We will have several speakers and we will end with a demo session. This will be the agenda for the evening: RISC-V Overview - Ted Speers, Microchip and RISC-V Foundation Board Software State of the Union - Palmer Dabbelt, SiFive Security Verification - Jason Oberg, Tortuga Logic Tyler Baker, foundries.io Dr. Martin Scott, Rambus Q&A Moderated by Ed Sperling Palmer is currently the RISC-V Software Team Lead at SiFive, where he maintains the RISC-V ports of binutils, GCC, glibc, Linux, and QEMU. Palmer got involved in the RISC-V project when he was a graduate student at UC Berkeley, where he worked on a pair of RISC-V chips and contributed to the RISC-V software ecosystem. He began his career at Tilera, where he spent most of his time working on a port of Sun's HotSpot Java virtual machine to a pair of Tilera's ISAs. In addition his MS in Computer Science from UC Berkeley, Palmer holds a BS in Electrical Engineering from the University of Illinois. Tyler Baker is CTO at Foundries.io Dr. Martin Scott is CTO at Rambus Dr. Oberg is one of the co-founders and Chief Executive Officer of Tortuga Logic. He oversees technology and strategic positioning of the company. He is the founding technologist and has brought years of intellectual property into the company. His work has been cited over 700 times and he holds 6 issued and pending patents. Dr. Oberg has a B.S. degree in Computer Engineering from the University of California, Santa Barbara and M.S. and Ph.D. degrees in Computer Science from the University of California, San Diego. Ed Sperling is the editor in chief of Semiconductor Engineering as well as a technology industry veteran and moderator and speaker in Silicon Valley. Ed previously worked as a contributing editor for Forbes, covering business and technology issues affecting IT and CIOs. Directions: Rambus is conveniently located in Moffett Towers off highway 101 and 237 / Mathilda Ave. in Sunnyvale, across from Moffett Field. From Enterprise Way, take either the second or third driveway on your right to enter the parking lot. Parking is free with a lot of available space, plus a covered parking garage and charging stations. Enter the ground floor lobby of the building from either door on the Enterprise Way street side of the building. After you enter the ground floor lobby, take one of the elevators up to the 7th floor Rambus lobby (no card entry required). All elevators go to the 7th floor. Link to Map: https://goo.gl/maps/ckakqVxnL9F2
- June Bay Area RISC-V Meetup
Save the date for the next RISC-V Meetup - June 19! This event will be hosted by SiFive! We will start with a networking session. The following are the topics and speakers planned for the evening: - Commercial Software Tools - Larry Lapides, Imperas - Securing RISC-V Processors - Dan Ganousis, Dover Microsystems - Extending Unleashed with AI Accelerators - Palmer Dabbelt, SiFive About Larry: Larry is VP of Sales at Imperas. Prior to joining Imperas, Larry ran sales at Averant and Calypto Design Systems. He was vice president of worldwide sales during the run-up to Verisity's IPO (the top performing IPO of 2001), and afterwards as Verisity solidified its position as the fifth largest EDA company. Before Verisity and SureFire (acquired by Verisity), Larry held positions in sales and marketing for Exemplar Logic and Mentor Graphics. Larry was recently an Entrepreneur-in-Residence at Clark University's Graduate School of Management, where he developed and taught a course on Entrepreneurial Communication and Influence. Larry holds an MBA from Clark University in addition to his MS Applied & Engineering Physics from Cornell University and BA Physics from the University of California Berkeley. http://www.imperas.com/ About Dan: Dan is currently the Director of Sales at Dover Microsystems. He began his 40-year career in the semiconductor industry working on the design, test, and manufacturing of the Z80, 65C02, MicroVAX, and Solbourne microprocessors. He moved into sales and marketing in the EDA industry where he held executive positions at Mentor Graphics, Viewlogic, and VeriBest before assuming the CEO position at startups AccelChip and Arithmatica. Most recently Dan was a business development consultant for embedded processor IP vendors Codasip, Cortus, and Andes. Dan holds a BSEE degree from Rensselaer Polytechnic Institute.www.dovermicrosystems.com About Palmer: Palmer is currently the RISC-V Software Team Lead at SiFive, where he maintains the RISC-V ports of binutils, GCC, glibc, Linux, and QEMU. Palmer got involved in the RISC-V project when he was a graduate student at UC Berkeley, where he worked on a pair of RISC-V chips and contributed to the RISC-V software ecosystem. He began his career at Tilera, where he spent most of his time working on a port of Sun's HotSpot Java virtual machine to a pair of Tilera's ISAs. In addition his MS in Computer Science from UC Berkeley, Palmer holds a BS in Electrical Engineering from the University of Illinois. https://www.sifive.com/
- Inaugural Bay Area RISC-V Meetup!!!
Please join us for the inaugural Bay Area RISC-V Meetup! We will start out with a networking session, including refreshments. Talks will include an introduction to the RISC-V Foundation, an overview of RISC-V and a RISC-V technical discussion (subject TBD). We will update the agenda within the next week.