Join us for the second Bristol RISC-V Meetup!

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Following our successful first Bristol RISC-V Meetup last October, we are pleased to invite you to join us at our second one, which will be jointly hosted by UltraSoC and Imperas Software!

The evening will start at 6pm with a networking session, including refreshments. We will have a number of engaging talks, and there will also be live technical demonstrations.

There will be some interesting speakers, including:

Dr Carl Shaw – Cerberus Laboratories, Co-Founder
Dave McEwan – EPSRC Centre for Doctoral Training in Communications, PhD student
Mark Hill – Huawei, Chief CPU Architect
Simon Davidmann – Imperas Software, Founder and CEO
Gajinder Panesar – UltraSoC, CTO
Ben Marshall – University of Bristol, Research Associate

This Meetup will take place in the events room on the 4th floor of DeskLodge at Temple Way, a short walk from Bristol Temple Meads station.

Places are limited, so please book soon! We look forward to seeing you there.

Please visit https://riscv.org/ for more information about RISC-V, and to read how, as a member of the RISC-V Foundation, UltraSoC is deeply involved in developing and defining the debug architecture for RISC-V standards, visit https://www.ultrasoc.com/technology-2/risc-v/. Imperas helps RISC-V developers with virtual platforms and tools for early software development, RISC-V compliance testing and test development. Visit http://www.imperas.com/imperas-riscv-solutions

You may like to check out our blog post from our first Bristol RISC-V Meetup: https://www.ultrasoc.com/the-rising-temperature-of-risc-v-in-bristol/.

Also, if you are interested in speaking at a forthcoming RISC-V Meetup, please do get in touch by sending an email to [masked]. This community is to provide an open platform for all in which to share experiences, to build understanding and open doors to opportunities based on the RISC-V architecture.