For our last Meetup of 2015 we're excited to have Krste Asanović, a Professor in the EECS Department at the University of California, Berkeley present and lead a discussion about The RISC-V Instruction Set Architecture. Please join us as we dive into the world of open source ISA's and IoT.
We're also happy to announce a raffle giveaway. Three lucky attendees will win a 3 month package of free Neo connectivity (25$ value) for your IoT devices. For more on Neo visit http://neo.aeris.com/
6:30 PM Pizza & Networking
6:45 PM Audience Announcements
7:00 PM Presentation followed by Q&A
8:00 PM Networking
8:30 PM Close
Hope to see you there!
What is RISC-V?
"RISC-V (pronounced "risk-five") is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education, which we now hope will become a standard open architecture for industry implementations. RISC-V was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley."
"Our intent is to provide a long-lived open ISA with significant infrastructure support, including documentation, compiler tool chains, operating system ports, reference software simulators, cycle-accurate FPGA emulators, high-performance FPGA computers, efficient ASIC implementations of various target platform designs, configurable processor generators, architecture test suites, and teaching materials. Initial versions of all of these have been developed or are under active development. This material is to be made available under open-source licenses."
The most important interface in a computer system is the instruction set architecture (ISA) as it connects software to hardware. So, given the prevalence of open standards for almost all other important interfaces, why is the ISA still proprietary?
* There is no good technical reason not to have free, open ISAs just as we have free, open networking standards and free, open operating systems.
* The most likely first target for a free, open ISA are systems-on-a-chip for the Internet-of-Things, which have low cost and power demands, yet require extensive software stacks.
* The best architectural style for any free, open ISA is RISC.
* Given the time it takes to design an ISA, it makes more sense to adopt an existing RISC free, open ISA than to design a new one from scratch.
* Among the existing RISC free, open ISAs, RISC-V is the best and safest choice.
To learn more, see www.riscv.org
Krste Asanović is a Professor in the EECS Department at the University of California, Berkeley. He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005. He returned to join the faculty at Berkeley in 2007, where he co-founded the Berkeley Parallel Computing Laboratory ("Par Lab"). His main research areas are computer architecture, VLSI design, parallel programming and operating system design. He is currently Director of the Berkeley ASPIRE lab tackling the challenge of improving computational efficiency now that transistor scaling is ending. He leads the free RISC-V ISA project, is Chairman of the RISC-V Foundation, and has recently co-founded SiFive Inc. to support commercial use of RISC-V processors. He is also an Associate Director at the Berkeley Wireless Research Center, and holds a joint appointment with the Lawrence Berkeley National Laboratory. He received the NSF CAREER award, and is an ACM Distinguished Scientist and an IEEE Fellow.