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Parag

Location:

San Jose, CA

Member since:

September 16, 2013

What would you like to get out of this meetup?

Learn new concepts of UVM/OVM based verification and network with other verification Engineers

How much experience do you have with SystemVerilog? Don't be modest.

approximately 1 and a half years. Working as a Verification Engineer for the last one year

What are the ideal locations/times for you, for such meetups?

monday to thursday after 6pm

Would you or your employer be willing to host an event or provide a projector?

no

Will you be attending DVCon this year and able to attend a meetup one day? http://dvcon.org/

yes

Introduction

I have completed my Masters in Electrical Engineering specializing in Digital Design and Verification. Currently working as a Junior Design and Verification Engineer.


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