8B/10B Line Coding, Vivado's Timing Path Report

CadHut - Sydney: FPGA and circuit design
CadHut - Sydney: FPGA and circuit design
Public group

Location visible to members

What we'll do

This month will cover why DC-balanced line codings like 8B/10B exist, where they are used and how they work.

We will also have a (fairly short) session, showing how to make sense of Vivado's timing path report.

If there's time, we may cover an older topic for people who have joined recently.

We're lucky to be back in Data 61's offices in Redfern. Please arrive before 6:30pm; the presentation starts