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Announcing tinyML EMEA Innovation Forum 2022 on October 10-12, 2022 (https://www.tinyml.org/event/emea-2022)
Connect, Unify, and Grow the tinyML EMEA Community.
This event will be held in person in Cyprus.
The tinyML EMEA Innovation Forum 2022 brings together key industry leaders, technical experts, and researchers, from Europe, the Middle East, and Africa (EMEA) region, innovating with machine learning and artificial intelligence on ultra low-powered devices.
Tiny machine learning combines innovation across a deep technological stack ranging from dataset collection and ML application design, through innovative algorithms and system-level software, down to hardware and novel sensor technology. As a cross-layer technology, achieving good results in tinyML requires carefully tuning the interaction between the various layers, and designing systems with a vertically integrated approach. In the EMEA region many startups, established companies, universities, and research labs are investing substantial time and effort in developing novel advanced solutions for tinyML. We hope you’ll join us as the tinyML EMEA Innovation Forum aims to connect these efforts, find strength in unity, and cooperate to accelerate tinyML innovation across the region.
Registration is open: https://www.jotform.com/222084960021144
Sponsorships are available: https://www.tinyml.org/news/tinyml-emea-innovation-forum-2022-sponsorship-opportunities
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Announcing tinyML Talks on October 13th, 2022
IMPORTANT: Please register here
Once registered, you will receive a link and dial in information to teleconference by email, that you can also add to your calendar.
8:00 AM - 9:00 AM Pacific Daylight Time (PDT)
Kaiyuan Yang, Assistant Professor, Rice University
Weier Wan, Head of Software-Hardware Co-design, Aizip
"Processing-In-Memory for Efficient AI Inference at the Edge"
Performing ever-demanding AI tasks in battery powered edge devices requires continuous improvement in AI hardware energy and cost-efficiency. Processing-In-Memory (PIM) is an emerging computing paradigm for memory-centric computations like deep learning. It promises significant energy efficiency and computation density improvements over conventional digital architectures, by alleviating the data movement costs and exploiting ultra-efficient low-precision computation in the analog domain. In this talk, Dr. Kaiyuan Yang will share his research group’s recent silicon-proven SRAM-based PIM circuit and system designs, CAP-RAM and MC2-RAM. Next, Dr. Weier Wan will introduce his recent RRAM-based PIM chip, NeuRRAM. Through full-stack algorithm-hardware co-design, these demonstrated PIM systems attempt to alleviate the critical inference accuracy loss associated with PIM hardware while retaining the desired energy, memory, and chip area benefits of PIM computing.
Dr. Kaiyuan Yang is currently an Assistant Professor of ECE at Rice University, USA. He received his B.S. degree in Electronic Engineering from Tsinghua University, China, in 2012, and his Ph.D. degree in Electrical Engineering from the University of Michigan, Ann Arbor, in 2017. His research interests include digital and mixed-signal circuit and system design for secure and intelligent microsystems, bioelectronics, and hardware security. Dr. Yang is a recipient of the 2022 National Science Foundation (NSF) CAREER award, 2016 IEEE SSCS Predoctoral Achievement Award, and multiple best paper awards from premier conferences in various fields, including 2021 IEEE Custom Integrated Circuit Conference i(CICC), 2016 IEEE Symposium on Security and Privacy (Oakland), 2015 IEEE International Symposium on Circuits and Systems (ISCAS), and the Best Student Paper Award finalist at 2022 RFIC and 2019 CICC.
Dr. Weier Wan is currently leading the software-hardware co-design and is a founding member at Aizip, a Silicon Valley startup providing TinyML solutions. He received his Ph.D. degree in electrical engineering from Stanford University in 2022, where he worked on designing efficient AI hardware system to enable intelligence at the edge. His research work has been published in top journals and conferences, including Nature, International Solid-State Circuits Conference (ISSCC), and Symposium on VLSI Technology and Circuits. He is the first author of a monumental work published in Nature this year, titled “A compute-in-memory chip based on resistive random-access memory”. Previously, he received his master’s degree in electrical engineering from Stanford University in 2018 and his bachelor’s degree in physics, electrical engineering and computer sciences from University of California, Berkeley in 2015.
We encourage you to register earlier since on-line broadcast capacity may be limited.
Note: tinyML Talks slides and videos will be available on the tinyML website and tinyML YouTube Channel afterwards, for those who missed the live session. Please take a moment and subscribe to the YouTube channel today: https://www.youtube.com/tinyML?sub_confirmation=1