Name: Munich RISC-V 3rd Meetup (second virtual)
Start: 2020-06-25T16:00:00+02:00
End: 2020-06-25T18:00:00+02:00

📣Register here to join online:
https://attendee.gotowebinar.com/register/3590939412782896395

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We will have a number of interesting speakers and also give a RISC-V overview! As it is a virtual conference we will make it 2h.

We plan some Q&A, you can submit questions during the presentation and we will answer them via chat or live from the speaker.

📅 AGENDA OVERVIEW

💻 Overview to CHIPS Alliance & RISC-V SweRV Cores
Zvonimir Bandic, Western Digital

💻 A visual simulator for teaching computer architecture using the RISC-V instruction set
Guillaume Savaton , ESEO

💻 On-Chip Instrumentation – Debug & Trace, and On-Chip performance monitors
Gajinder Panesar, UltraSoC

💻 What's missing in RISC-V Linux, how YOU can help!
Björn Töpel, RISC-V Enthusiast

💬 Q&A's

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We are still looking for speakers, so if you have an speech in the area of RISC-V feel free to contact us via Message or email florian (at) andestech (dot) com.
This time we think to limit it to 4 speaker but we already look for speaker for the next time, so feel free to submit your speech (or speech idea)
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Flo Wohlrab

Rachel Miaou

Munich RISC-V Group

Technology

Architecture

New Technology

Microcontrollers

Hardware Engineering

Computer Science

Software Architecture

Computers

Embedded Systems

Technology Startups

Verilog

System on Chip

Open Source Hardware

Computer Architecture

Software and Hardware