FPGA-aften 2026 uke 8: LiteX RISC-V MCU

Vi leker med, og deler kunnskap om, feltprogrammerbare portmatriser.
Ta gjerne med egne prosjeker for å vise fram.
Alle som er interesserte i FPGA er velkomne.
De som er nye på Bitraf får en introduksjon og omvisning av stedet vårt.

Jon Nordby vil forklare kort hvordan man:

• Definerer en RISC-V-mikrokontroller med LiteX,
• definerer egne FPGA-periferer laget med Verilog+migen, og
• får tilgang til periferene gjennom minnet fra frittstående C-programmer.

Kode og notater finnes i dette arkivet:
https://github.com/jonnor/embeddedml/tree/master/handson/fpga-riscv

English:

We play with, and share knowledge on, field-programmable gate arrays.
You're welcome to bring any projects to show off.
Everyone interested in FPGA is welcome.
Those who are new to Bitraf are offered an introduction to, and tour of, our space.

Jon Nordby will briefly cover how to:

• Define a RISC-V microcontroller SoC with LiteX,
• define custom FPGA peripherals made with Verilog+migen, and
• access the memory mapped peripheral from bare-metal C programs.

We will use the Lattice ICE40UP5k FPGA with the fully open source yosys+nextpnr
workflows. But the approach should be applicable to any FPGA supported by
LiteX.

Code and notes in this repository:
https://github.com/jonnor/embeddedml/tree/master/handson/fpga-riscv

Image License:

BSD 2-Clause License

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FPGA based systems.

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