June Austin RISC-V Meetup hosted by SiFive
Details
Please join us for the next Austin RISC-V Meetup. We will begin with a networking session, followed by presentations. Anyone interested in the RISC-V ISA and related ecosystem is encouraged to attend!
Presentations will include:
>> FROM A CUSTOM 2 SERIES CORE TO 'HELLO WORLD' IN 30 MINUTES
(Drew Barbier, SiFive)
Drew will walk through configuring a custom E2 core using SiFive Core Designer, and then use Freedom Studio to write software targeting the custom core in the included RTL testbench and on an FPGA.
www.sifive.com
>> SOLUTIONS FOR DEBUG & ANALYTICS IN HETEROGENEOUS SOCS
(Randy Fish, UltraSoC)
SoCs are a mix of processors today. Many chips today include RISC-V, ARM, Tensilica, MIPS, … all within the same design. UltraSoC will describe RTL IP and software solutions that enable debug and analytics throughout the life of an SoC from simulation to emulation to in-lab to in-life.
www.ultrasoc.com