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Agenda

5:30-6:30 Networking

6:30-7:10 SweRV Core Architecture – Robert Golla, Western Digital

7:10-7:35 Achronix FPGAs, SweRV place & route – Joseph Krensavage, Achronix

7:35-8:00 Securing RISC-V cores – Cesare Garlati, HexFive

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