Cache Coherent Memory Fabric based on RISC-V

Note the new link to register!!!
Because we have a large number of attendees, we are requiring a bit more security. You must go to this link to obtain the meeting information. The old zoom link is no longer valid! https://zoom.us/webinar/register/WN_YXrqU5rqRmWFgju_h2G-kg

With RISC-V being an open ISA, this has enabled many open system architectural capabilities. One of these is the cache coherent Tilelink bus. Based on Tilelink, an open cache coherent memory fabric call OmniXtend was developed. This online meetup will discuss the latest updates, support and next steps for this revolutionary architecture.

5:45-6:00 - Login & say hello to each other
6:00-6:20 - TileLink Introduction - Wesley Terpstra , SiFive
6:20-6:40 - OmniXtend Overview - Zvonimir Bandic, Western Digital
6:40-7:00 - Tofino Programmable Switch OmniXtend - Curt Beckmann, Intel
7:00-7:20 - Latest developments & next steps
7:20-7:30 - Remaining Q & A

You can download the updated Outlook ics file for this online meetup. Click this Box link - https://wdc.box.com/s/k3j0j5k5jx0jxgxqxjrzyx4rl9pu9hbn