Production grade, open RISC-V SweRV Core Solutions in CHIPS Alliance
Details
This online meeting features presenters who can explain how to implement the production grade, open RISC-V SweRV Core into your design.
Start time: May 20, 2020 at 5:30pm Pacific
Intro to CHIPS Alliance & SweRV family overview – Zvonimir Bandic, BoD CHIPS Alliance (15 mins)
SweRV EH2 /EL2 architecture – Robert Golla, Western Digital (20 mins)
SWeRV and open source tooling ecosystem – Michael Gielda, Antmicro (20 mins)
SSP, SweRV Support Package for commercial support – Codasip (15 mins)
Simulator in Google Cloud for SSP – Metrics (15 mins)