Sneak Peek at Makerchip

This meeting will be exciting for me. It's my chance to show off the latest from Redwood EDA -- Makerchip. Makerchip is our not-yet-released online Integrated Development Environment for Verilog design. I'm very proud of it, and I'm happy to see growing interest from members of the meetup.

I used Makerchip in the "Newbies" session to teach logic design basics in a hands-on way. A couple of the participants asked if there were opportunities to go further with it, and I know a few experienced folks are also interested in playing with it. I mentioned, in last night's meetup, the idea of starting up a users' group and working on some open source projects, and I got a good response, so it looks like a go.

This meetup session will introduce makerchip.com and for folks interested in the users' group, this will be a good lead-in. This is a chance to learn to design with capabilities that are both easier and more powerful than the ones used in industry today.

We'll walk through design exercises similar to the ones that can be found in our work-in-progress tutorials at http://makerchip.com/tutorials . Participants should be familiar with the basics of digital logic. Those who are already familiar with Verilog will have a headstart in some ways but should be willing to unlearn a few things that aren't needed in this environment (such as always blocks, blocking vs. non-blocking assignments, reg vs. wire, generate blocks, etc.).

Bring a laptop running a modern web browser. Chrome is our development platform. (IE is not a modern browser.)

More about Makerchip:

Current industry tools and languages are very powerful, but they are also bloated, difficult to learn, and require installation and administration. Makerchip introduces not only easier design methods, but more powerful ones as well. It is a clean re-think, with the developer in mind, implemented using modern web and cloud technologies. Oh, and it's free for all to use!

Makerchip supports Verilog and SystemVerilog, but its power and simplicity are unleashed by a new evolution of Verilog, called Transaction-Level Verilog. TL-Verilog enables digital logic to be expressed succinctly (half the size), within the context of pipelines and transactions. This context provides organization and enables you to reason about and manipulate your design at a higher level.

https://a248.e.akamai.net/secure.meetupstatic.com/photos/event/7/1/7/4/600_456149044.jpeg Makerchip is targeted for release in early 2017, but you can test drive at http://makerchip.com/sandbox in the meantime. If you can't wait for the meetup, try our WIP tutorials (http://makerchip.com/tutorials) (and please provide feedback).

More about the Users' Group:

The User's Group will be an opportunity to share and learn design skills from others. You'll have a chance to contribute to an emerging open source ecosystem for IC design (OpenCores (http://opencores.org/), RISC-V (https://riscv.org/), LibreCores (https://www.librecores.org/)). And you'll be an active part of the Redwood EDA story as it unfolds. The feedback and insight Redwood will gain from early users is immeasurable and will have a significant impact on our success. And the skills you will learn and the contacts you will make could open doors.

I hope you join us at this exciting time. For now, I will run this group as part of this meetup series, but it may naturally evolve into a separate entity over time.