Speaker: Steve Hoover, Redwood, EDA
Type of Course: Self-paced, on demand Course. Lab format
Dates: 3/1/21 - 3/31/21
Course Overview: CPUs are a fundamental building block of complex SoCs, and RISC-V is taking hold as the ISA of choice. In this workshop, you will create a Verilog RISC-V CPU from scratch, and you will modify this CPU to be suitable for different applications.
You will learn and use modern techniques, using Transaction-Level Verilog to generate and modify your Verilog code more reliably, in far less time. You will discover how concepts like pipelining and hazards can be incorporated easily using timing-abstract design principles.
All labs will be completed online in the Makerchip.com IDE for open-source circuit design. The skills you learn will be applicable far beyond CPU design.
Course Format:
- self paced, on demand course, providing attendees a flexible schedule
- access to content for 30 days
- pre-scheduled live Zoom and chat sessions with instructors during the 30 day access period
- offline chat available with instructors during the entire 30 day access period (reply within 24 hours).
Target Audience: Engineers interested in a career in digital logic design or adjacent disciplines, including experienced engineers looking to modernize their skill set.
Prerequisites: An engineering education and basic understanding of digital logic. (Verilog knowledge is not a prerequisite.)
Registration will be available soon.
Members: $350.00
Non-Members: $395.00
