What we're about

This group is for anyone interested in the open source RISC-V instruction set architecture (ISA) and related ecosystem.

For more information on RISC-V please check out the RISC-V Foundation @:


Upcoming events (1)

4th RISC-V Israel Virtual Meetup

Online event

Please join us for the 4th RISC-V meetup in Israel, hosted by Imperas, Syntacore and Western Digital, with an agenda that will cover WD and the latest SweRV cores release, Imperas on RISC-V vectors, verification and virtual platforms, and Syntacore updates on open source and commercial RISC-V cores. The event will conclude with the traditional question and answer session with the presenters. Agenda: 5:45-6:00 – Login & Hello 6:00-6:25 – Overview to CHIPS Alliance & RISC-V SweRV Cores, Zvonimir Bandic, Western Digital 6:25-6:50 – Imperas and RISC-V: Vectors, Verification and Very Early Software Development, Larry Lapides, Imperas Software 6:50-7:15 – RISC-V IP solutions open source & commercial, Ekaterina Berezina, Syntacore 7:15-7:30 – Q&A ***The lectures will be held in English*** PLEASE PRE-REGISTER AT https://us02web.zoom.us/webinar/register/8915936848258/WN_uOXxPHuQSJi3-HvuOh3zNw

Past events (8)

3rd RISC-V Israel Virtual Meetup

Online event

Photos (12)