meet Hardware Description Language VHDL

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Details

using VHDL we can easily implement our own hardware (yes! a Video Card, an I/O controller, and even our own processor with our own instruction set) on a programmable gate arrays (FPGAs).

Topic:

In this meeting we will try to create a simple RISC processor that can execute our own instruction set (very few instructions) and see how it works on a real hardware (e.g. Terasic DE1-SoC with Altera FPGA).

Instruction set:

1) LOAD (constant to Accumulator register),

2) DECREMENT (of Accumulator's contents),

3) CONDITIONAL JUMP (Jump if not zero - JNZ after last arithmetic operation like DECREMENT),

4) UNCONDITIONAL JUMP

Program that we will try to execute:

first_program: LOAD 5
loop: DECREMENT
JNZ loop
JUMP first_program

The contents of Accumulator register will be displayed on 7-segment displays in HEX, and the processor execution modes will be: maximum speed (1MHz), or 1 instruction per button click.

The SignalTap analyzer will be used to see state transitions of processor's FSM and analyze signal delays.

Meetup plan:

First, a presentation will be given on basic constructs of VHDL. Then, we will have hands-on session to code an FSM for our processor. All other codes, as well as a backup code for working FSM will be provided. IDE is Altera's Quartus II 15.0 Web Edition, which will also be provided for at least two PC's.

This meetup requires only slight knowledge of boolean operations, all other necessary info will be given.

The given code will be able to execute just NO_OPERATION and HALT instructions. During each of the hand-on sessions the task will be to implement additionally: LOAD_ACCUMULATOR, DECREASE_ACCUMULATOR, JUMP and JUMP_IF_NOT_ZERO instructions.