FPGA Workshop #2 - build & simulate a RISC CPU

".. all workshop materials are available online at https://github.com/makehackvoid/fpga-sig/tree/master/2018_cpu/

"In workshop #2 we will be looking to add a register file and a control ROM to our design. With these components in place we can then start executing complete instructions. Right now this will be limited to 3 instructions, no-operation (NOP), load immediate (LDI) and logical and (AND).

"To understand the register file we are going to need to know about sequential logic. This means learning about flip-flops and state machines.

"To make sense of what I’ve mentioned above I will talk a little about RISC instruction sets, instruction formats and the AVR instruction set.

"What you need to bring:

• A laptop or computer with Xilinx Vivado installed https://github.com/makehackvoid/fpga-sig/blob/master/2018_cpu/docs/lab01.md
• Warm clothing, the space can get chilly this time of year

"If you missed workshop #1 you are welcome to attend. You’ll need to work through Labs 2-5 before attending. I have posted solutions in the code section of the repository so reading through should be enough to get you up to date. Last sessions lecture slides are available as a PDF: https://github.com/makehackvoid/fpga-sig/blob/master/2018_cpu/docs/ws01.pdf

See you there!
Stephen"

Please visit https://forum.makehackvoid.com/t/saturday-4-august-1-5pm-fpga-workshop-2/1552 for more information

Image courtesy Thomas Lok https://www.flickr.com/photos/thomaslok/3613323728