Virtual Workshop: Using Intel® oneAPI Toolkits with FPGAs

Registration link: https://software.seek.intel.com/LPE_June26workshop

After you register for the workshop by using the link above, you will receive a confirmation email with more details about how to join the virtual workshop.

Agenda:
1/ 9:30 AM – 11:00 AM: Slides: Introduction to FPGAs, and Using Them with Data Parallel C++
2/ 11:00 AM – 12:00 PM: Lab: Practice the FPGA Development Flow
3/ 12:00 PM – 1:00 PM: Slides: Introduction to Optimizing FPGAs with the Intel oneAPI Toolkits
4/ 1:00 PM to 2:00 PM: Lab: Optimizing the Hough Transform Kernel

Important Notes:
1/ Please make sure you request DevCloud access with the code FPGA0626 if you want to participate in the hands-on workshop and follow along the coding exercises.
https://intelsoftwaresites.secure.force.com/devcloud/oneapi?elqTrackId=826cac01e153476ca859dce5fe9c02d2&elqaid=32882&elqat=2

2/ Join our Discord channel where our experts will answer your questions, and you can interact with other like-minded developers.
https://discord.com/invite/VVvk2bP

3/ During lab time, you can take a short break/getting lunch etc. and continue working.

Abstract:
FPGAs are powerful hardware accelerators that can be configured into custom solutions, such as speeding up key workloads and adapting to emerging standards or changing requirements. The Intel oneAPI Toolkits allow developers to develop, optimize, and deploy algorithms that use Intel FPGAs as look-aside accelerators in a compute system.

In this tutorial, you will learn to write and compile Data Parallel C++ (DPC++) code to target an Intel FPGA. You will learn and practice the development flow to (1) emulate your code to ensure functionality, (2) optimize your code using reports, and (3) generate and profile the hardware bitstream created from your code.

You will also be introduced to the concepts and strategies needed to ensure your code is optimized for performance. A hands-on lab will take you through multiple stages of optimization of example DPC++ code.

The hands-on lab portion of this tutorial will make use of the Intel DevCloud. You will receive instructions and practice on the use of the Intel DevCloud during the tutorial.

Speaker: Susannah Martin
(bio) Susannah Martin is a senior applications engineer in the customer training group for Intel FPGAs. In the training group, she loves teaching others and increasing their knowledge of FPGAs. She is responsible for developing and maintaining the Intel training material on FPGA high-level tools, as well as SoC related training content. Prior to becoming a trainer, she worked as an FPGA design engineer, embedded programmer, and field applications engineer.

Topics to be covered:
• Write DPC++ code to target an FPGA
• Understand the flow to target DPC++ code to an FPGA
• Understand how your code is compiled into an FPGA design incorporating a Custom Compute Pipeline
• Understand and be able to write your kernel scope code as a task
• Examine an FPGA optimization report and analyze many performance bottlenecks
• List several techniques to optimize your command group scope code

Length of the tutorial: 4.5 hours

Format of the tutorial: Webex for presentation portion, Intel DevCloud accessed through browser for labs