Cont'd discussion on the open core UART test plan

I would like to cont'd discussion on the UART test plan ( https://www.amazon.com/clouddrive/share?s=i99feYohRkwpbcHMIOfDxw) which will have significant impact on how the UVM test bench being designed.

In the above test plan, you will see few underline clauses which will have implications on how the test bench should be structured to allow the re-usability and randomization.