Name: Accelerate Verification of RISC-V Ariane design with VerifAI's AI Test Engineer
Start: 2024-06-18T18:00:00-07:00
End: 2024-06-18T20:00:00-07:00

Abstract: [VerifAI Inc](https://www.verifai.ai). has pioneered the world's first '[AI Test Engineer'](https://www.youtube.com/watch?v=ah4dyu9Spl0) called [TestGuru](https://testguru.ai) which leverages Multiple Large Language Models (LLMs), Reinforcement Learning (RL), and Formal Methods to find and fix bugs in code while improving coverage and speeding up verification by 100x.

TestGuru comprises three components: CodeGuru, SimulationGuru, and DebugGuru.

This talk will demonstrate how VerifAI's tools can generate UVM tests for the RISC-V Ariane Design.
We will showcase VerifAI's VSCode Plugin and illustrate its capabilities in automatically generating UVM tests for the RISC-V Ariane design, as well as explain and analyze the Verilog code.

We will discuss how VerifAI's SimulationGuru improves coverage on the RISC-V Ariane Design's Data-Cache.
Specifically, we will present a use case focused on increasing the 'victim buffer count' in the Data-Cache, highlighting the practical application of VerifAI's technology in improving the verification and testing process for complex hardware designs.

**Author Bio:**
**Sandeep Srinivasan**, CEO VerifAI Inc. Sandeep is a serial entrepreneur, he has founded 4 startups. His previous 2 startups (Mskribe Inc and Synchronous Design Automation) have been in the space of algorithms to Reduce power consumption on complex IC’s. Sandeep also founded a consumer facing location based Messaging startup that uses machine learning to keep track of your friends and family. Two of the startups Sandeep started, were acquired by larger companies. Sandeep’s expertise is in Building Products, Teams and companies from Ground up. His technical expertise is broad , in the areas of Machine Learning, CAD , Graph Algorithms, Microprocessor Design, Software Architecture. Sandeep started his career in the Microprocessor group @AMD, and held Senior R&D management positions at Cadence Design Systems, Ammocore, InTime Software and HLDS. Sandeep has a MS EE/CS from U Wisconsin Milwaukee and LEAD Program from Stanford Business School. Sandeep holds multiple patents in the area of location based messaging and machine learning for verification and medical applications.

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Bay Area RISC-V Group

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Accelerate Verification of RISC-V Ariane design with VerifAI's AI Test Engineer

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Accelerate Verification of RISC-V Ariane design with VerifAI's AI Test Engineer

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