FPGA meetup with Espen Tallaksen from EmLogic

We get a visit from Espen Tallaksen from EmLogic.

He will start with a lecture for students (9-11) and then for the FPGA group (12-14). You can attend both if you want.

09:00-11:00 Guest lecture for students, but open to anyone
Making a simple testbench - step-by-step (2 * 45 minutes)
Most simple testbenches have close to no structure, are terrible to modify and hopeless to understand. On top of that, they take far too much time to implement and provide close to no support when debugging potential problems.
This presentation will show and exemplify how to build a far better testbench with respect to all these issues, in significantly less time. The presentation will also explain how this verification approach even results in reduced design time and reduced debug time. The examples will show testbench code using UVVM (Universal VHDL Verification Methodology)
UVVM Utility Library is open source and should really be used by anyone making a VHDL testbench (unless they have a better system available). UVVM was first released in April 2013 and is today being used by more than 27% of all FPGA designers and 25% of all ASIC designers worldwide.
Verification is critical knowledge for an FPGA designer today – and thus very important also for students.

FPGA group 12-14

**Assertions in VHDL and UVVM (**Same as for FPGA-forum)
Assertions can be very useful in detecting problems in your design – and maybe even more important – detecting problems early where the problem arises. Assertions could be used in your design, typically to check assumptions, integration, relations, etc, but also in your testbench, typically to verify specific temporal properties. This presentation will show the use of simple assertions for static and dynamic properties for both design and verification. There will be examples using pure VHDL assertions and the new assertion library in UVVM.
Get the right FPGA quality through efficient Specification Coverage (aka Requirement Coverage)
Specification coverage is getting more and more attention, and is critical for safety (e.g. DO-254) and mission critical (e.g. ESA space and Avionics) applications.
Unfortunately, this is often handled manually, which is very time-consuming and error-prone. UVVM’s Specification coverage allows a really efficient collection of predefined requirements, and it generates the reports you need for both mission-critical and safety projects, and in fact for any project where quality is important.
This presentation gives a brief overview of Specification Coverage before going into more details of proper Requirements Tracking. It also shows what is provided with UVVM and how this could be applied. UVVM is free and Open Source, and so are all the interface models, randomisation, functional coverage and specification coverage.