Summer of TL-Verilog Encore Presentations

We've gone quite a while without a meetup. I've been busy working with several students this summer on open-source TL-Verilog projects sponsored by Google Summer of Code. In the process, we've put together a number of conference papers and presentations. We may as well repeat them.

1. I presented "Overcoming RTL: The Most-Adaptable Open-Source RISC-V Core" at DAC 2018 in June.
2. Akos Hadnagy presented "Formal Verification of WARP-V, a TL-Verilog RISC-V Core Generator" at ORConf 2018 in Sept., and he will deliver a similar presentation soon for VSDOpen 2018.
3. Ahmed Salman will present "Top-Down Transaction-Level Design with TL-Verilog" at VSDOpen 2018.
4. I will present a few slides to kick off the VSDOpen 2018 Front-End Symposium, describing industry trends that are transforming the silicon industry.

We'll do a presentation marathon... or let's say an evening conference, delivering all four with a bit of time for Q/A and discussion.

We'll get pizza as usual.

I look forward to seeing you all again!