An MLIR Pipeline for ComputeRAM: Enabling Compute-in-Memory IP

Hendrik Klug is joining us to give a talk on the work he has been doing at Synthara to enable their in-memory compute IP using an MLIR-based stack.

As usual there will be pizza, snacks, beer, and soft drinks after the event for participants, sponsored by Prof. Zhendong Su and the Advanced Software Technologies (AST) Lab at ETH Zurich.

Abstract: Licensing custom accelerators as IP to chip makers comes with all sorts of challenges for the compiler. In particular, compute-in-memory hardware moves computation into the memory hierarchy, which requires a different kind of scheduling than conventional compilation pipelines usually perform. Synthara's computeRAM is an in-memory compute IP that is integrated into a wide range of targets, from smartwatches to datacenter accelerators, and each chip maker brings their own toolchain. So computeRAM has to come with a compilation pipeline flexible enough to plug into whichever platform compiler the chip maker is developing, schedule the memory hierarchy and compute capabilities exposed by the hardware, and stay maintainable as the IP evolves. MLIR's dialect and transformation model lets us integrate into the customer's compilation pipeline rather than replace it, and the same pipeline can be retargeted as the integration surface changes from one chip maker to the next. In this talk we walk through the MLIR pipeline we have built around computeRAM at Synthara: the hardware and the platforms it integrates into, the lowering pipeline to both LLVM and EmitC, and the optimizations we do for computeRAM. Throughout, we share what we learned: the good, the bad and the ugly of what's available upstream.

Location: The event is taking place in the room G51 in the CAB building of ETH Zurich at the Zentrum campus. Enter from Universitätstrasse 6.