Name: Event #4: Processor Performance Insights and Optimization
Start: 2024-11-06T17:00:00+01:00
End: 2024-11-06T21:00:00+01:00
Location: Kista Science Tower

More details and registration here:

[https://kista.com/events/casa-meetup/](https://kista.com/events/casa-meetup/)

We have two excellent presentations:

**"The Intel Processor Tracer and its use cases", from Bogdan Tanasa.**

In this presentation I will show how I used the Intel Processor Tracer (IPT) for different purposes like building the flow of a program and performing instruction tracing on real hardware (that supports the IPT). I will also present some more general ideas for tooling based on IPT that could ease performance bottleneck investigations. The Intel Processor Trace (Intel PT) is a powerful hardware-based tracing feature that enables the capture of detailed instruction execution information with minimal performance overhead. It provides an in-depth view of program execution by recording control flow changes such as branches, exceptions and interrupts, which are crucial for debugging and performance optimization in complex systems. The IPT allows you to record the control flow of programs so that more complex analyses can be performed offline.

*Bogdan Tanasa is Senior Software Engineer currently affiliated with Wind River. Previously he worked at Ericsson and SAAB. He holds a PhD in real-time systems given by Linköping University.*

**"Why Moore's Law Makes Microcode a Good Idea", by Stefan Blixt.**

This talk will provide an overview of the architecture and programming model of the Telesis Universal System-on-Chip (USOC), which features a unique processor design allowing post-manufacturing customization. It is based on microprogrammed control of a small, flexible machine, suitable for both high- and low-level processing. It aims at the highly diverse, multi-billion units per year IoT/OT device market. The processor is distinctive for very good reasons, which will be detailed during the presentation. It is, however, rooted in classic concepts and has been well-proven across various embedded applications. These applications typically combine high-level language, graphics, media processing, and input/output, offering high code density, efficiency, reliability, and low system cost.

*Stefan Blixt is the founder and CEO of Telesis Innovation. He previously founded Imsys, and has extensive experience in radar data processing, graphics and image processing, precise timing, and dataflow processing. He has 67 patents and has been recognized with invention grants from the National Swedish Board for Technical Development. He is currently seeking partners to collaborate on a new processor architecture designed for modern CMOS technology and SoC components capable of media processing and AI/ML.*

Jakob Engblom

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Event #4: Processor Performance Insights and Optimization

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Event #4: Processor Performance Insights and Optimization

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