IEEE - Princeton / Central Jersey Section

PRINCETON ACM / IEEE COMPUTER SOCIETY
OCTOBER 2025 JOINT MEETING

Computer Graphics Film Show -- SIGGRAPH Video Review

Note location change: Friend Center, lower level, room CS004.

It's time again to kick off our season of meetings with the annual computer graphics film show, featuring the latest and greatest computer animations direct from the ACM SIGGRAPH conference held this summer. (We have been running a graphics talk each year since 1980! This year is our 46th!) It will be an entertaining overview of recent advances in computer graphics.

The meeting will start 15 minutes early - several of our chapter members will remember a long-time friend of our chapter, Norm Badler, who passed away in May 2025. Norm had a 50-year career at University of Pennsylvania, and he was active in the field of computer graphics.

Date: Thursday October 16, 2025, 7:45 PM EDT (Norm Badler remembrance), 8:00 PM EDT (Graphics talk)

(Note: Refreshments and networking start early - 7:30 PM.)
Place: HYBRID MEETING (both in-person and online)
In Person: Princeton University Friend Center, Room CS004
79 William St., Princeton NJ
(NOTE: We are **not** our normal room in the CS building this year - this room it is in the lower level of the Friend Center - enter on William St.)

IEEE Princeton / Central Jersey Section, Life Members, present:

"From Enigma to Now: A Journey Through Wireless Security" - Joe Jesson

ABSTRACT: Joseph discusses wireless security beginning with WWII enigma code interception and decryption methods along with the heros and heroines who worked around the clock to save the allied nations. The cold war, following WWII, introduced additional risks and new challenges and, by example, wireless security failures, ease of wireless packet intercept, and a list of encryption methods with inherent security defects. Finally, wireless risks present in 2025 are shown as security aircraft, ship, automotive, and military cases aircraft, drones, and ship examples. IMSI-catcher is a telephone eavesdropping device used for intercepting mobile phone traffic and tracking location data of mobile phone users. A "fake" base station may be installed in a building, state police trunk, or UAVs and Balloons (!) and targeted cell phones acquired, tracked, & logged. This mapping and the service provider's real towers is considered a man-in-the-middle (MITM) attack. However, sophisticated attacks may be able to downgrade 3G and LTE to non-LTE network services - which do not require mutual authentication - and calls intercepted. State-of-the-art 5G Cellular security technology and the identified risks of base-station's dynamically changing protocols, hardware BTS trojans, and group cellids and location interception challenges are highlighted. Originally presented at a Rutgers IEEE dinner, a professor commented it would be a sleepless night after hearing the risks outlined!

SPEAKER'S BIOGRAPHY: Joseph Jesson, is CEO of RFSigint Group, a wireless sensor platform IP and SOC supply-chain advisory company, Adj ECE Professor at The College of New Jersey, and currently consults with corporations on wireless sensor networks (LPWAN narrowband digital technology). Joe has 25+ years of experience in designing and implementing - through production - IoT wireless sensors & embedded systems and was awarded General Electric's Innovation prize, the Edison Award, in 2007. Joe was awarded over 15 patents, published in the IEEE IoT Journal, and engineered and tested wireless TEMPEST-shielded secure systems. Currently IEEE Princeton LIFE Affinity Group Chair.

Date and Time
Date: 22 Oct 2025Time: 07:00 PM EDT to 08:30 PM EDT

"High-performance Energy-efficient Compute-in-Memory and AI accelerators for sub-18A Technologies" - Dr Ram Krishnamurthy

Abstract: This presentation will highlight some of the emerging challenges and opportunities for sub-18A process machine learning and AI technologies in the rapidly evolving semiconductor industry. With Moore’s law process technology scaling well into the nano-scale regime, future SoC platforms ranging from high performance cloud servers to ultra-low-power edge devices will demand advanced AI capabilities and energy-efficient deep neural networks. New and emerging AI markets from data centers to wearable devices will require even higher performance at much lower cost while reducing energy consumption. Some of the prominent barriers to designing high performance and energy-efficient AI processors and SoCs in the sub-18A technology nodes will be outlined. New paradigm shifts necessary for integrating special-purpose machine learning accelerators into next-generation SoCs will be explored. Emerging trends in SoC circuit design for machine learning and deep neural networks, specialized accelerators for digital and analog in-memory and near-memory computing, reconfigurable multi-precision matrix multipliers, ultra-low-voltage logic, memory and clocking circuits, AI inference accelerators including binary neural networks and associated on-chip interconnect fabric circuits are described. Future brain-inspired neuromorphic computing circuit design challenges and technologies will also be reviewed. Specific chip design examples and case studies supported by silicon measurements and trade-offs will be discussed.

Speaker's Biography: Dr. Ram K. Krishnamurthy is Intel Fellow at Intel Corporation, Intel Labs, Office of the CTO. In this role, he is responsible for research in high performance energy efficient integrated circuits for future CPUs, GPUs, AI processors and accelerators across data center to edge computing platforms. He has 27+ years of experience and deep expertise in Systems-on-Chip (SOC) design in leading-edge semiconductor technologies. Since 1997, he led circuit technology research and made major contributions to Intel data center, client, GPU, FPGA, edge IoT, and AI products portfolio spanning twelve generations of silicon processes. Dr. Krishnamurthy has filed more than 350 patents and holds over 200 issued patents. He has published 200 papers in premier IEEE conferences and journals. He is a recipient of two Intel Achievement Awards (Intel Corporation’s highest technical award), Intel Labs Gordon Moore Award, Intel inventor awards for highest number of patents filed and issued, Distinguished paper award from IEEE International Solid State Circuits Conference, Outstanding industry mentor award from Semiconductor Research Corporation, Best paper award from IEEE European Solid State Circuits Conference, Distinguished alumni award from State University of New York, Alumni recognition award from Carnegie Mellon University, and MIT Technology Review TR35 innovator award. He was recognized as a top contributor in IEEE International Solid State Circuits Conference’s 70 years publication history. He is a Fellow of the IEEE. Dr. Krishnamurthy served as Chair of Semiconductor Research Corporation Technical Advisory Board AMS-CSD. He was General Chair and Technical Program Chair of IEEE International Systems-on-Chip Conference and is currently on the Steering Committee. He served as guest editor of the IEEE Journal of Solid State Circuits, associate editor of the IEEE Transactions on VLSI Systems, and on the technical program committees of ISSCC, CICC, ESSCIRC, and SOCC conferences. He was distinguished lecturer of IEEE Solid State Circuits Society and adjunct faculty of electrical and computer engineering at Oregon State University, where he taught advanced VLSI design. He is a board member on various industry advisory boards. Dr. Krishnamurthy received the B.E. degree in electrical engineering from National Institute of Technology, Trichy, India, in 1993, M.S. degree in electrical and computer engineering from State University of New York at Buffalo in 1994, and Ph.D. degree in electrical and computer engineering from Carnegie Mellon University in 1997.