Multi-Level Rewriting for Stream Processing to RTL compilation

Abstract:
High-level synthesis (HLS) mainly aims to map sequential programs to hardware and seldomly considers alternative input types. Even though
sequential programs have parallelizable parts, they are inherently not
a good match for the massively parallel hardware on which HLS tries
to map them. Some HLS tools have libraries that help encode paral-
lelism in the input language, but they are combined with C-like input
and require plumbing to integrate it into existing systems. Instead
of consuming C as an input language, this thesis proposes a stream-
ing abstraction (essentially a domain-specific language) that encodes
thread parallelism directly and can be lowered to heavily pipelined
circuits. To achieve this goal, we introduce compiler transformations
that extend a dataflow abstraction used in dynamically scheduled HLS
to support pipelining and build the streaming abstraction on top of it.
This work demonstrates that the usage of domain-specific abstractions
for hardware is a way to simplify hardware compilation substantially.
The resulting hardware circuits consume data at line rate, i.e., at the
maximum achievable bandwidth, without user interaction during
compilation

Speaker:
Christian Ulmann