Modern Vector Instructions: Compilation & Code Generation & Hardware Design

In three tech-talks we discuss modern vectorization in depth from compiler representation, instruction set design, down to to hardware implementation. With Simon Moll, Robin Kruppe, and Matheus Cavalcante we host experts from Saarbruecken, Darmstadt and Zurich.

Talk 1: EVL -- Bringing LLVM's IR up to speed with vectorization.

There has been a recent surge in vector ISAs, let it be the RISC-V V
extension, ARM SVE or NEC SX-Aurora, all of which pose new demands to
LLVM IR. Among their novel features are an active vector length, full
predication on all vector instructions and a register length that is
unknown at compile time. In this talk, we present the Explicit Vector
Length extension (EVL) for LLVM IR. EVL provides primitives that are
practical for both, backends and IR-level automatic vectorizers. At the
same time, EVL is compatible with LLVM-SVE and even existing short SIMD ISAs stand to benefit from its consistent handling of predication.

Simon Moll is a fourth-year PhD student at Saarland University. He is best
known for his work on the Region Vectorizer (RV), which brings
Outer-Loop and Whole-Function Vectorization to LLVM IR with ISPC-like
control-flow handling.

Talk 2: RISC-V Vectors in LLVM

The vector extension, called 'V' for short, adds standardized vector processing capabilities to RISC-V. Similar to other modern vector architectures such as Arm's Scalable Vector Extension (SVE), it supports a wide range of processor designs by allowing the maximum size of a vector to be determined at run time rather than being fixed at design time. These variable vector lengths, and other features driven by the need to support many different applications and microarchitectures, pose new challenges for compilers. This talk discusses some of these challenges as well as the work happening in LLVM to address them, both to support variable-length vectors in general as well as the particulars of RISC-V vectors.

Robin Kruppe is an M.Sc. student at TU Darmstadt in the Embedded Systems and Applications group. He is a member of the working group defining the RISC-V vector extension and active in the LLVM community, leading the development of LLVM support for that extension.

Talk 3: ARA: 64-bit RISC-V Vector Implementation in 22nm FDSOI

In this talk, we detail our experience in the design and
implementation of the RISC-V Vector Extensions (v0.4 draft) in an
advanced silicon process. ARA is a high-performance vector co-processor
soft core that attaches to and cooperates with an existing open-source
RISC-V core Ariane, implementing RV64GC.

Matheus Cavalcante is a PhD Student at the Integrated Systems Laboratory of ETH Zurich, under the supervision of Professor Luca Benini, working on HPC devices, specifically vector processors.

Videos of previous talks:

http://pollylabs.org/llvm-social-zurich.html

Where:

ETH Zurich, CAB, E72

The building closes at 19:00. If you are late, you need to write us to be let in.

What is LLVM:

LLVM (http://www.llvm.org/) is an open source project that provides a collection of modular compiler and toolchain technologies. It is centered around a modern SSA-based compiler around which an entire ecosystem of compiler technology was developed. Most well know is the clang C++ compiler, which is e.g. used to deploy iOS. Beyond this a diverse set of projects is developed under the umbrella of LLVM. These include code generators and assemblers for various interesting architectures, a jit compiler, a debugger, run-time libraries (C++ Standard Library, OpenMP, Opencl library), program sanity checkers, and many more. LLVM has itself grown out of a research project more than 10 years ago and is the base of many exciting research projects today:

https://scholar.google.ch/scholar?cites=7792455789532680075&as_sdt=2005&sciodt=0,5&hl=de

Contact:

Tobias Grosser (https://www.inf.ethz.ch/personal/tgrosser/)