How the chip design industry works + Verilog interview prep for the students

An electronic education event in Los Angeles hosted by the Verilog Meetup club which usually meets in Silicon Valley. We created Verilog examples that are used by more than 20 universities worldwide. We welcome people with different expertise levels, from those just curious about how the industry that produces smartphones and other electronics works – to EE and CS students, as well as career changers interested in how to practice for job interviews in electronic companies (microarchitecture, RTL, design verification). In addition to the discussion, we will bring FPGA boards suitable for training future ASIC designers. So bring your laptops – we want you to play and tweak some electronic designs.

In more detail:

Verilog Meetup is an electronic education community that meets every Sunday in Silicon Valley and over Zoom – with participants on all continents. We create Verilog examples that universities use to teach Electrical Engineering and Computer Architecture labs. We run seminars, help to prepare for job interviews, and explore new chip design methodologies.

For our offline session in Los Angeles, we welcome both beginners and people with experience in ASIC and FPGA design, system design and verification.

• For the beginners we are going to give an inside of how the chip is made: the basis of the technology (RTL-to-GDSII design flow) and the distribution of roles in the design team.
• For the students and graduates, we will discuss how to practice for an interview with electronic companies by solving microarchitectural problems and doing open-source projects on FPGA boards.
• In addition to slides, we will demonstrate and let the participants play with the boards with the chips from Gowin. While we use FPGAs from all major vendors (Xilinx/AMD, Intel/Altera, Gowin, Lattice and Efinix), we particularly like Gowin for fast synthesis and the option to use open-source toolchains.
• We will also touch on open-source ASIC design tools, the Open Lane toolchain, and demonstrate how to use it to syhthesize a minimalistic CPU.

See you at the event!

To cover renting the space, it is a paid event. You can pay here or register at Eventbrite:

[https://www.eventbrite.com/e/verilog-meetup-in-la-how-a-chip-is-designed-tickets-998861951987](Please register at Eventbrite)

A footnote for the beginners:

“Verilog, ASIC, FPGA” are not exactly household words, but they are at the very heart of the microelectronics revolution that brought us smartphones, fast internet, 3D graphics and AI acceleration. For the last 40 years, the Verilog hardware description language has been used to design the logic of chips. An ASIC (Application Specific Integrated Circuit) is the chip itself, and an FPGA (Field Programmable Gate Array) is a chip used to prototype an ASIC.