SYCL: a programming standard for heterogeneous computing based on modern C++

Heterogeneous computing is now the norm for systems ranging from low-end embedded devices up to the high-end HPC systems to reach high-performance while keeping power consumption low.

Programming multi-processor system-on-chips with different kinds of processors, graphics processing units (GPU), configurable specific accelerators (video CoDec, machine-learning accelerators...), reconfigurable programmable logic (FPGA), coarse-grain reconfigurable arrays (CGRA), various hierarchies of memory and memory interfaces, configurable I/O and network support, security support, power control, etc. is a real challenge.

This presentation covers the SYCL programming standard from the Khronos Group (http://sycl.tech) which aims to solve some of these programming issues.

SYCL is a domain-specific embedded language based on pure modern C++ allowing you to write single-source C++ host code with accelerated code expressed as lambdas or classes. SYCL defines a few classes to provide the minimal concepts needed to add heterogeneous computing in C++: devices, queues, memory buffers, ...

The data accesses are described with accessor objects that implicitly define a task graph that can be asynchronously scheduled on a distributed-memory system including several CPU and accelerators.

SYCL provides a fall-back mode for execution on CPU when no accelerator is available or to ease development and debugging on a standard computer by leveraging the usual development tools since SYCL is just pure C++.

Several implementations are available, most of them open-source, targeting CPU (with OpenMP & TBB), GPU (with OpenCL/SPIR, Vulkan or CUDA), FPGA and other accelerators.

• Speaker Bio

Ronan Keryell is principal software engineer at Xilinx Research Labs, where he works on high-level programming models for heterogeneous system, such as FPGA, with the open-source SYCL implementation.

He is the specification editor of the SYCL standard, member of the SYCL, SPIR & OpenCL standard committees from Khronos Group & ISO C++ committee.

Ronan Keryell received his MSc in Electrical Engineering and PhD in Computer Science from École Normale Supérieure of Paris & University of Paris Sud (France), on the design of a massively parallel RISC-based VLIW-SIMD graphics computer (a Jurassic GPU ancestor...) and its programming environment. He spent some time in the academia working on automatic parallelization, compilation of PGAS languages (High-Performance Fortran), high-level synthesis and co-design, networking and secure computing. He was co-founder of 3 start-ups, mainly in the area of High-Performance Computing, and was the technical lead of the Par4All automatic parallelizer at SILKAN, targeting OpenMP, CUDA & OpenCL from sequential C & Fortran. Before joining Xilinx, he worked at AMD on programming models for GPU.