RISC-V SweRV Core Deep Dive

Western Digital recently open sourced the first production grade RISC-V core, the SweRV Core EH1. At this meetup, the architecture details on this 32 bit core will be discussed. Technical experts will explain the tradeoff decisions made when developing the SweRV Core EH1, targeted applications and a technical code walk through will be shown.

Agenda:
5:30-6:30 Networking & Refreshments
6:30 SweRV Core Architecture Deep Dive
7:00 SoC Level Analytics, Trace & Debug for SweRV Core Designs