UCSC Extension Community

 
 
 

Learn how to prepare and apply the S.T.A.R. method for interviews and prepare for the many types of questions you may be asked in an interview at this hour-long, in-person event with Michael Carmine, a UCSC Extension Career Engagement specialist.

This is a drop-in event hosted by the International and Career Teams at UCSC Extension.

All are welcome!

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Join us for a free, half-day workshop on the key concepts of an ASIC design physical implementation flow using OpenROAD. OpenROAD delivers a fast, barrier-free, and low-cost RTL-to-GDS, no-human-in-loop flow for design above 12nm and is one of the tools students can work with in UCSC Silicon Valley Extension VLSI Engineering program courses
Knowing how to use open EDA tools boosts your career prospects in the exponentially growing semiconductor industry!
In this workshop, you’ll:

• Explore the design space for QoR estimation and implementation.
• Analyze key design parameters early in the RTL design phase for fast convergence to performance, power, and area targets.
• Leverage the cloud and other collaborative tools to optimize computational resources for fast run times and efficiency.

Workshop Topics

• < 24 hrs, No-human-in-loop, RTL to GDS flow in OpenROAD
• RTL architectural exploration for a good floorplan
• Timing analysis using OpenSTA
• Incremental design optimization
• Verifying your design - DRC and LVS checks
• Using metrics to track QoR improvements
• OpenROAD applications

Who should attend?

• Students of digital design, verilog design, physical design, and timing closure courses
• Experienced professionals working in the VLSI chip design space looking to upskill
• Hardware designers looking to innovate at the systems level
• Software engineers seeking to learn hardware design and leverage tools for design productivity in a semiconductor design team

Presenters

• Matt Liberty, V.P of Engineering, Precision Innovations Inc.
• Indira Iyer Almeida, Head of User Experience and Outreach, Precision Innovations Inc.

This event is co sponsored by the UCSC Silicon Valley Extension VLSI Engineering program.

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We will talk briefly about how Cadence applies its underlying Intelligent System Design™ strategy to deliver software, hardware, and IP that turn design concepts into reality.

We will then take a deep dive into Cadence Cerebrus, an AI-enabled chip design optimization tool that provides improved power, performance and area along with a 10x to 20x productivity boost by leveraging machine learning for synthesis, place, and route.

Presenter
Sajan Sahili, MSEE, Principal Product Engineer at Cadence Design Systems
Sajan supports the Digital Signoff group products. She joined Cadence as an intern about eight years ago and is involved in customer engagements for Innovus. She works to debug design issues to achieve the best performance of chips and identifies enhancements needed for Cadence tools. She also works on Cerebrus enablement and has led many successful Cerebrus engagements for key customers achieving and exceeding power, area, and timing goals. In her personal life, she is the mother to a four-legged fur ball and likes to travel and read fiction.

This event is sponsored by the VLSI Engineering certificate program at UCSC Silicon Valley Extension and is one of a series of VLSI workshops scheduled for 2023.

To keep up with VLSI events, please join our LinkedIn Group—VLSI Chip Design Silicon Valley—UCSC Extension, or sign up for our bi-monthly newsletter.

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10 Days in Silicon Valley to change your life.

Together with TiE Global we've launched Destination Silicon Valley, a new business accelerator program to propel startup entrepreneurs to their next level.

You'll get personalized mentorship with Silicon Valley CEOs, investors, and business leaders, while you build out your vision for a successful venture.

• Sharpen your business model.
• Execute your plan.
• Perfect your pitch.

Limited enrollment.
$[masked]

Learn more about this new bootcamp at https://www.ucsc-extension.edu/…/destination-silicon-valley/