Name: RISC-V meetup: Enhancing convolutional neural network computation
Start: 2024-08-15T17:00:00-07:00
End: 2024-08-15T19:00:00-07:00
Location: Rivos 4th Floor

We have two presentations confirmed so far.

**Topic#1:** Enhancing convolutional neural network computation with integrated matrix extension
This proposed architecture introduces a novel matrix extension and customized quantization instructions for RISC-V CPUs, specifically targeting general convolutional neural network (CNN) applications. Key elements include:

1. **Matrix Multiplication/Accumulation Instructions:**

* Designed to be VLEN agnostic, ensuring scalability and portability across diverse VLEN machines.
* Aim to increase computing capacity and compute intensity while reducing memory access bandwidth requirements.

2. **2D-Load/Store Unit (LSU):**

* Facilitates matrix tiling enhancements.
* Includes Zero-Overhead Boundary handling to streamline user configuration cycles.

3. **Novel Quantization Instruction:**

* Accelerates the entire CNN computation process.
* Contributes to significant performance enhancements when integrated with other advanced techniques.

**Performance Enhancements:**

* **Kernel Loop MAC Utilization Rate:** Surpasses 75%.
* **Compute Intensity:** Achieves up to 9.6 (VLEN 512), thanks to advanced software unrolling techniques.
* **General Matrix Multiply (GeMM) and CNN Workloads:** Preliminary performance data highlights notable benefits and potential acceleration.

This architecture demonstrates the potential to significantly enhance the performance of CNN applications on RISC-V CPUs by integrating these state-of-the-art techniques.

**Speaker's Bio:**
Bing Yu is a Sr. Technical Director at Andes Technology. He has over 30 years of experience in technical leadership and management, specializing in machine learning hardware, high performance CPUs and system architecture. In his current role, he is responsible for processor roadmap, architecture, and product design. Bing received his BS degree in Electrical Engineering from San Jose State University and completed the Stanford Executive Program (SEP) at the Stanford Graduate School of Business.

**Topic#2:** Empowering the Future: Unveiling Next-Generation RISC-V Devices

**Abstract:** This talk covers 2024 latest RISC-V powered mass produced products from AI speakers to laptops, most importantly soon coming AOSP lastest Android 15 support Pad in Q4, as well as motherboard for Framework DIY laptops by going an upgradable/affordable modular approach to help scaling up end user bases crossing various communities from Framework, RISC-V, Ubuntu and Fedora communities.

**Speaker's bio:**
Yuning Liang is the Founder and CEO of DeepComputing, focusing on developing innovative technology products based on RISC-V SoMs. From the world's first RISC-V development laptop DC-ROMA to pads, workstations, remote-controlled cars, drones, and more, all are based on RISC-V chips.
The world's first RISC-V laptop, the world's first RISC-V pad capable of making phone calls, and so on, are all Yuning's masterpieces. Yuning's innovation and pioneering spirit in the RISC-V field have enabled him to create several world firsts, leading DeepComputing to gain widespread recognition in the global RISC-V product commercialization field, contributing significantly to the advancement and progress of RISC-V technology.
Yuning's career has taken him from the UK to Switzerland, then to South Korea, and finally to China. He has a strong practical background in embedded systems, platform APIs, and system software.

PS: Food and beverage will be provided.

Aditya

Bay Area RISC-V Group

Technology

New Technology

Hardware

Embedded Systems

Open Source Hardware

Software and Hardware

Android

System on Chip

RISC-V meetup: Enhancing convolutional neural network computation

Rivos 4th Floor

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Bay Area RISC-V Group

RISC-V meetup: Enhancing convolutional neural network computation

Bay Area RISC-V Group

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