November RISC-V Bay Area Meetup hosted by Antmicro

Attend the last RISC-V Bay Area Meetup before the Inaugural RISC-V Summit in December and listen about new and exciting open source developments in the ecosystem, including Google's TensorFlow Lite on RISC-V, Antmicro's Renode and more!

Schedule:

6:00-7:00 Networking with appetizers and beverages
7:00-8:30 Speakers/Demo

"TensorFlow Lite on RISC-V" (Pete Warden - Google)

Many emerging new microcontrollers use RISC-V, and the TensorFlow Lite team has been exploring how to best support these new platforms. In this talk, Pete Warden, Lead of the TensorFlow Mobile/Embedded team at Google will discuss how they've used Renode, gcc, and other open-source technologies to target RISC-V for machine learning.

"Design Cycle Acceleration for HW/SW Co-Design with Renode" (Michael Gielda – Antmicro)

Embedded systems design that involves "whole stack" co-design, including hardware, firmware, runtime (OS), and development toolchain, presents novel engineering challenges. Traditional hardware-led approaches do not work, as the software and toolchain need to co-evolve with the hardware.

Dover Microsystems faced such challenges when implementing a cybersecurity product that involves both silicon IP and runtime & toolchain modifications. Dover is using the Renode open source functional simulation framework (https://renode.io) to drastically reduce their design cycle and rapidly explore architecture trade spaces. In addition, the approach enables Dover to provide a simple and effective means for customers to evaluate the entire solution, and to begin adapting their software collateral in parallel with the hardware integration effort.

Antmicro will present a case study of how open-source, extensible, debuggable, and robust functional simulation has been critical to Dover’s success, and why Dover thinks Renode should become a standard part of all hardware and embedded system design and development efforts.

"Making RISC-V The Most Secure Platform" (Cesare Garlati - Hex Five Security)

In this session industry veteran Cesare Garlati, co-founder of Hex Five and Chief Strategist at prpl Foundation, will share the latest on RISC-V security and will offer his practitioner advice for developing secure applications. Garlati will start with an explanation of the security building blocks defined by the ISA including privileged modes and physical memory protection. He will then show how to combine these blocks to develop trusted applications with particular emphasis on IoT devices that lack MMU – and this is the capabilities of RISC-V especially shine. Finally, Garlati will introduce a breakthrough system design philosophy, entirely based on free and open standards, that allows hardware-enforced software-defined separation of data, programs and peripherals for an unlimited number of trusted execution environments.

"Tim has too many projects! (RISC-V Edition)" (Tim 'mithro' Ansell - TimVideos)

Tim is a long time member of the Australian open source community, where he is known for regularly giving 5 minute lightning talks with 100+ slides called "Tim has too many projects" (and way to many slides)!

Having managed to escape the deadly wildlife he will now present a much more leisurely whirlwind tour through the many hardware projects he is involved with and how they now somehow all end up using RISC-V too, including:

HDMI2USB (https://hdmi2usb.tv) - An open source FPGA based, conference and user group capture hardware used to record conferences around the world.

LiteX Build Environment (https://github.com/timvideos/litex-buildenv/wiki) - A Python system for fast creation of architecture independent "soft CPU" based systems.

FuPy (https://fupy.github.io/) - A project to allow you to do full stack development (FPGA gateware & CPU firmware) in Python!

Tomu (https://tomu.im) - Open hardware microcontroller system inside your USB port and maybe now with more RISC-V? Come find out!

There may even be hardware giveaways and crazy announcements!