Verilog Meetup #6

This is a follow-up from Verilog Meetup #5

https://www.meetup.com/hackerdojo/events/298923812/

Verilog Meetups #6 and #7 will take place on Sunday, March 3rd and March 10th, from 2pm to 5pm

CPU: simulate, synthesize, and implement in ASIC and FPGA

During the two upcoming Verilog meetups, we will get a simple RISC-V assembly program together with the most basic CPU core possible and run the following:

1. A simulator on Instruction Set Architecture (ISA) level, RARS.
2. A simulator on Register Transfer Level (RTL), Icarus Verilog.
3. An FPGA synthesis flow for Xilinx, Altera, and Gowin.
4. An ASIC synthesis flow using Open Lane.
5. A GCC compiler to see how C code maps into RISC-V assembly.

Eventually, we will use this setup to do a whole bunch of experiments
with the CPU cores: add instructions, use arithmetic blocks, and
memories with different latencies, modify the pipeline, add caches, and
create multi-core configurations.

You can read more details here - http://habr.com/en/articles/796255

See you on Sunday!