Chips @ Dojo: Open Source Design Verification
Details
This is a non-commercial technical meetup focused on the progress of open-source silicon design and verification tools. As part of the community energy around DVCon week, we aim to gather specialists to share results on making chip design more accessible. Technical Scope Toolchains: Verilator, SVALint, Verible (Google), UVMLint, and Slang.
Demos: Porting industry-standard protocols (AXI/AHB/APB) to open-source environments and automated testbench generation. Additional presentations: Verilog Meetup materials developed at Hacker Dojo, including SystemVerilog Microarchitecture Challenges for AI. Format: Hybrid event.
No ticket required to attend. Entry is free, with an optional $20 donation to support Hacker Dojo. For those who prefer, a limited number of $30–$40 tickets will also be available.