What we’re about
The goal of the group is to create a set of portable SystemVerilog examples to use in educational seminars worldwide on digital design and microarchitecture. The focus is on solving three challenges:
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Removing EDA and FPGA vendor lock for the educators. The examples support 30 boards with FPGAs from Xilinx, Altera, Gowin and Lattice and aim to be compatible with open-source ASIC design tools.
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Compensating the gap between academia and industry in solving microarchitectural problems necessary for a career in ASIC design, building CPU, GPU and networking chips.
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Reducing the barrier of entry for the novice or a person from a related field aiming to extend their expertise to become better in system design or software acceleration.
