Maximize RISC-V Performance with Custom Design

Maximize RISC-V Performance with Custom Design | Oct 7 | Milpitas

Join Andes Technology for a free in-person RISC-V technical workshop on October 7, 2026, at SEMI in Milpitas.

Hear practical insights on custom instructions, Memory performance, and RISC-V Vector optimization.

Talk Sessions

• 10:30 AM — Andes: your Commercial-Grade RISC-V Processor IP Partner — Emerson Hsiao
• 10:40 AM — Unlocking SoC Performance with RISC-V Custom Instructions — Darren Jones
• 11:10 AM — Hitting the Memory Wall: CPU Performance Beyond Compute — Mia Chang
• 11:40 AM — DGEMM Optimization & RISC-V Vector Performance — Trevor Cooper
• 12:10 PM — Lunch & Networking

📍 SEMI, Milpitas
🎟️ Free to attend
🚗 Free parking
🍽️ Lunch provided
🤝 Technical sessions + networking
Registration is required and subject to approval.
Register:https://www.eventbrite.com/e/maximize-risc-v-performance-with-custom-design-tickets-1999406122535?aff=Meetup